1. Field of Use
The present invention relates to electronic integrated circuits (ICs) and, more particularly, to circuits which employ a standard boundary scan test access port.
2. Prior Art
A standard boundary scan test architecture was approved by the American National Standards Institute (ANSI) and the Institute of Electrical and Electronics Engineers (IEEE) in 1990. This architecture provides a means by which ICs may be designed in a standard fashion such that they or their external connections, or both, may be tested using a four or five wire interface.
The roots of boundary scan testing are found in the scan test methodology developed in the 1960s. An example of one implementation of this technology is described in U.S. Pat. No. 3,582,902, granted Jun. 1, 1971. The basic scan concept is to join all storage elements (e.g., flip-flops) of a logic design in one or more serial strings. The serial, or shift register, interconnection is in addition to the normal functional interconnection, and is intended to be primarily used during testing. Although this hardly makes the testing of complex systems easy to accomplish, scanning reduces the overwhelming chore from simulating sequential systems to the more manageable chore of simulating combinatorial systems.
It is important to note that the addition of scan circuitry does not benefit the functional role of the logic system to which it is added. Test circuitry is deemed undesirable overhead which would not be included if there were other practical ways of eliminating faults. Therefore, test simplification is a powerful economic incentive.
The complexities which arise from the use of the basic scan concept were the motivation behind the development of the boundary scan test architecture. Developing a test for a design using the original scan concept required simulating large sections of a system, or an entire system. During diagnosis, failing tests often could not be readily correlated with actual faults. The reason was that any one error indication sensed at the test system could be the result of one or more of a large number of faulty devices or interconnects, even when it was assumed that the integrity of the scan string was in tact (i.e., provided a fault free path).
In the boundary scan test architecture, a serial string is placed at the periphery of the IC, independent of storage element locations. A four or five wire interface between the various ICs of a system so designed to include the boundary scan test architecture in conjunction with a test system allows separate and isolated testing of the ICs and the connections between them. The end result provides a much simplified correlation between failing tests and physical faults.
Until now, scan testing has been regarded as purely digital. While methods have been proposed to test analog devices in conjunction with digital scan testing, they all share the approach of converting analog signal levels to digital signal levels and vice-versa as part of the interface between the test system and the analog devices to be tested. Where such conversion must be avoided, separate interconnections from the digital serial string are made between the test system and the analog devices to be tested. In this case, the digital serial string serves merely as part of a routing control mechanism for the analog signals.
Although the ability to accomplish analog testing with the same overhead test circuitry as used for digital testing is most desirable, until now implementing such an arrangement has been generally viewed as impractical. For example, separate IEEE working groups are developing different digital and analog test bus standards. It is generally the view in the testing field that in-circuit testers will not be replaced regardless of strides made in boundary scan testing because analog device testing is beyond the reach of the standard boundary scan architecture. Position papers presented at the 1992 IEEE International Test Conference in conjunction with a panel on mixed signal testing (proceedings pp. 555-557) indicate separate package pins might be used in an analog test architecture for analog test purposes, in addition to the pins used in the boundary scan architecture.
Significant benefit would be derived if it was possible to test analog devices utilizing the four or five package pin overhead test circuitry already largely found acceptable in the industry used to accomplish digital testing via boundary scan. This could often eliminate the need for in-circuit test stations in manufacturing. Also, this could often avoid the use of test points to accommodate such analog testing in printed circuit board designs involving optimum miniaturization. Furthermore, this could allow for analog testing at the internal IC device level.
Accordingly, it is a primary object of the present invention to provide a method and apparatus for analog and digital signal processing by an interface generally compatible with a standard boundary scan architecture.
It is a further object of the present invention to provide a method and means of testing analog components and devices utilizing such interface in conjunction with current digital scanning techniques.
It is a still further object of the present invention to provide the method and means for an analog interface which has no significant detriment to the digital scanning techniques already in place.